The present invention relates to testing of complex combinatorial and sequential logic circuits embodied in large scale integration (LSI) and very large scale integration (VLSI) circuit devices.
A fault occurring anywhere in such a LSI or VLSI circuit device can have its effect propagated through a number of feedback loops formed of storage or memory elements in the sequential logic before reaching a testable output of the device. Level sensitive scan design (LSSD) rules were devised to eliminate the complications in testing caused by this propagation through the feedback loops. As described by E. B. Eichelberger and T. W. Williams in an article entitled "A Logic Design Structure for LSI Testability" on pages 462-468 of the Proceedings of the 14th Design Automation Conf., LSSD rules impose a clocked structure on the memory elements of logic circuits and require these memory elements be tied together to form a shift register scan path so that the memory elements are all accessible for use as both a test input or output point. Therefore, with the scan path, test input signals can be introduced or test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis.
Single or multiple scan paths can be provided under the LSSD rules. It has been suggested in an article by R. A. Feretich appearing on page 5414 of the May 1980 issue of the IBM Technical Disclosure Bulletin that control means can be provided for LSSD scan circuits to switch between single or multiple path modes of operation.
In using LSSD, a single stuck-fault model is used to generate the test patterns applied to the circuit, and output responses are collected after each test for comparison with the precalculated "good circuit" responses. It has been shown that such stuck-fault test generation is one of a class of difficult mathematical problems called NP-complete, where NP stands for non-deterministic polynomial time and complete meaning that a solution for one problem in the class could be extended to all. In all NP-complete problems the number of possible solutions grows spectacularly as the size of the problem increases. Therefore, the implication is that test generation computer times increase exponentially with the size of the circuit. In view of this, it appears that the best stuck fault test algorithms are only computationally feasible for fairly small or fairly simple networks and fault-oriented approaches become prohibitively expensive with the increasing circuit density of VLSI chips and modules.
It has been previously suggested that self-testing be employed in connection with LSSD to reduce the time it takes to generate the test patterns and to perform the testing. Self-testing involves the use of pseudo-random pattern generators and response compression structures that are built into logic circuit devices. Using such pattern generators and compression structures eliminates the computer time needed to generate the tests while placing these testing elements on the device containing the logic allows the application of vast numbers of test patterns to the circuits in a reasonable period of time. Potential compression methods for use during these testings include transition counting, as suggested by J. P. Hayes in an article entitled "Testing Logic Circuits by Transition Counting", FTCS-5, pages 215-219, June 1975, and more recently, signature analysis, as described by R. A. Frohwerk in "Signature Analysis: A New Digital Field Service Method", Hewlett-Packard Journal, Vol. 28, pages 2-8, May 1977.
Konemann, Mucha, and Zwiehoff describe incorporating the structure necessary to perform random stimuli signature analysis into the circuit device being tested in their papers "Built-in Logic Block Observation Techniques", 1979 IEEE Test Conf., pages 37-41, Cherry Hill, N.J., October 1979 and "Built-in Test for Complex Digital Integrated Circuits", IEEE J. Solid-State C., Vol. SC-15, No. 3, pages 315-319, June 1980. In the Konemann et al articles a shift register scan path is reconfigured to form a serially connected linear feedback shift register (LSFR) circuit that operates either as a random input signal generator or as a data compression circuit to perform self-test signature analysis. One of the circuits operates as an input signal generator while another of these circuits operates as an output response compressor. During a later test their roles may be reversed. However, at no point does either LFSR circuit simultaneously perform both the input and output functions during the self-test.
In co-pending U.S. patent application Ser. No. 440,065 filed on even date herewith and entitled "Parallel Signature Generation Circuits", a plurality of LSSD scan paths are connected in parallel between different stages of a pseudo-random source and data compression circuit.